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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] RE: twist on iSCSI asymmetric modelSee below... Charles Binford
> -----Original Message-----
I could agree with this IF we use the same rule as FCP's Write XFER_RDY Disable bit. When this bit is set, it tells the initiator that it shall send the first burst of data after the command, but before the XFER_RDY. The maximum size of the this first burst of data is set by a mode page. If the I/O is larger that the first burst maximum, the initiator shall wait for an XFER_RDY for the balance of the data. The key here is the target KNOWS ahead of time the maximum number of buffers that will be used per command on an unsolicited basis. This covers the latency issue with small writes. When the initiator sends the occasional large I/O, the first burst goes as normal, then the balance comes when the target asks for it, after it has had time to allocate the additional buffer space. > In this
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