RE: iSCSI CRC: A CRC-checking example

["Douglas Otis" <dotis@sanlight.net>]

Sanjay,

In short, the reflected table is likely to require fewer instructions to
implement a lookup than a non-reflected table.  Secondly, if the processor
is Little Endian, then the result is already in network order without byte
swapping.  Obviously this last point only helps if you are using a Little
Endian processor but this happens only once per packet whereas the lookup
may happen every byte.  Third, the inverted store improves the sensitivity
to the packet length.  All these Ethernet techniques seems to be good
things.  One difference however is the polynomial.

Doug

> The last line says
>  "but I suppose it is advantageous to do
> things the ethernet way."
> May I know in what ways it would be advantageous.
>
> Regards
> Sanjay Goyal
>
>
>
> -----Original Message-----
> From: CAVANNA,VICENTE V (A-Roseville,ex1)
> [mailto:vince_cavanna@agilent.com]
> Sent: Thursday, August 23, 2001 1:55 PM
> To: 'Douglas Otis'; CAVANNA,VICENTE V (A-Roseville,ex1); 'Julian Satran'
> Cc: 'Mark Bakke'; ips@ece.cmu.edu; 'Steve Blightman'; THALER,PAT
> (A-Roseville,ex1)
> Subject: RE: iSCSI CRC: A CRC-checking example
>
>
> Doug,
>
> If the transmit side CRC generator used for the frame check sequence the
> remainder of the polynomial division directly (without complementing) the
> receiver-side CRC checker would be expected to end up with zeroes after
> processing an error-free frame. Unfortunately the receiver side
> CRC checker
> would also end up with zeroes after processing a frame whose only "errors"
> are extra trailing zeroes. Thus this type of error would not be
> detected by
> the CRC checker.
>
> Note that the expected final state of the receiver-side CRC checker is
> expected to be zero if hte remainder is not complemented even though both
> transmit and receiver sides initialize their CRC register to 1s. It is the
> operation of complementing the remainder that causes the receiver
> to have a
> non-zero (but constant) ending state after processing an error-free frame.
>
> If I understand you correctly, you have described another type of
> error that
> would be undetected were the remainder not complemented. Whenever the
> receiver CRC register is in its zero state (perhaps partially through a
> packet) the receiver checker would be blind to extra zeroes
> inserted in the
> packet at that point. I agree.
>
> Again, the improved protection resulting from initializing the
> CRC to 1s and
> complementing the remainder is not important for iSCSI because the packet
> length can be checked independently but I suppose it is advantageous to do
> things the ethernet way.
>