effect of initializing CRC reg to 1's depends on implementation?

[vince_cavanna@agilent.com]

In working with Luben Tuikov to document the math behind the CRC I
discovered something that surprised me. I intend to study this further but
hope someone can save me work by pointing out that I am wrong (or right) and
offering some proof.

Consider two ways to implement the iSCSI CRC with a serial divider (see PDF
file):

1. divide the message directly using a serial circuit that, when its stages
are initialized to zeroes, simultaneously multiplies by x^32 and divides by
G(x).

2. pre-multiply message by x^32 and then divide the results by G(x) using a
serial circuit that, when its stages are initialized to zeroes performs a
division by G(x).

The two circuits, of course, produce the same results when they are
initialized to 0's.

In the approach in (1) initializing the register to 1's appears equivalent
(produces the same quotient; same remainder) to initializing the register to
0's and complementing the most significant 32 bits of the message prior to
processing.

In the approach of (2) such an equivalence does not appear true!

This means to me that it is meaningless to specify that the CRC must be
initialized to 1's unless we refer to a specific implementation which we did
not do in the iSCSI spec! What is troublesome is that I have seen claims in
the literature (and in one textbook on data communications) that
initializing the CRc to 1's is equivalent to complementing the most
significant n bits of the dividend for both implementations. I have also
seen the same claim with no reference to an implementation (e.g. iSCSI)
which would imply that the implementation does not matter.

The implementation that I have most often seen referred to is a parallel
version of (1) wherein n message bits are processed at one time;
fortunately, for such an implementatiaon, the claim appears to be correct.

Thanks. <<Scan_Fro.pdf>> 

Vince Cavanna
Agilent TEchnologies

Scan_Fro.pdf