RE: effect of initializing CRC reg to 1's depends on implementati on? iSCSI

[Luben Tuikov <ltuikov@yahoo.com>]

Hello Paul,

I like the current description of CRC32C of iSCSI, except
for one small little thing: page 194 of v9, dash 2:

  - the CRC register is initialized with all 1s (equivalent
     to complementing the first 32 bits of the message)

This is actually equivalent to XORing the first
32 bits of the message with the magic constant as Vince
and I have shown.

If this is changed, then the message in its form:
  M'(x) = x^32 M(x) + x^(32+n) I(x)

yields to better optimizations as Vince and I have shown.
(see his circuits and worksheet4.pdf, which I posted
yesterday)

I.e. the message is augmented (mult by x^32, aka postfixed)
and prefixed by 32 1's (aka CRC=32 1's).

From this M'(x) one can derive the Simultaneous Multiply
and Divide alogirthm (SMD), get the constants to which the
CRC has to be set or the first 32 MSb of the PDU, etc.

In an SMD, one would have to set the CRC to the magic
constant and then proceed as the algorithm indicates,
(this is identical to what you'd find in Ethernet,
and is derived from M'(x), as Williams [1] shows)

In a simple divide, one would have to Magic XOR 32 MSb of
PDU, CRC = 0 and then proceed.

Williams [1], shows how this is possible, in his paper, but
he doesn't use math to show how/why as the title of the
paper indicates (``Painless guide...''), and most
derivations are omitted.

Regarding examples: I like examples, we should have the
examples as they are in the draft, but fix the CRCs for
ones, decs and incs.

``A picture's worth a thousand words.''

-l

P.S. I've just got the math on the SMD, and will be
communicating it with Vince. A worksheet5.pdf will follow
with the math.

[1] Williams, Ross, Painless guide to CRC error detection
algorithms. Rocksoft.



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