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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: iSCSI: 12-97 Bit Rulepat_thaler@agilent.com wrote: > [cheerfully deleted 0-content reply] > On the particular text: > 8) The message sent is P and appended at the end are the > bit coefficients of CRC(x), with x^31 bit coefficient > first, then x^30, etc. > the problem is that the x^31 bit doesn't go first when it is in the frame. > Also, bits can go through their entire existence without being sent in > serial order so nothing is first. Say which bit of the CRC goes into which > bit of the digest field and you are done. Bzzt. Wrong. As you said, this is all hypothetical. Just as Julian said: ``hypothetical bit stream''. How did you get ``frame'' involved? You're mixing high-level, and low-level implementation. Once you have that bit stream ready and built, as outlined above by me, _THEN_ you pass it to the upper layers which will take care of sending and reordering, and what not. AND IF an implementation can ``see'' that it can optimize things just because their bit/byte order is such an such, then so be it, BUT the explanation should be formal enough and NOT refer to any particular implementation. -- Luben
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