Persistent, Protected and Cached: Building Blocks for
Main Memory Data Stores

Carnegie Mellon University Parallel Data Lab Technical Report CMU-PDL-11-114v2, Nov 2012. Supersedes CMU-PDL-11-114, Dec. 2011.

Iulian Moraru1, David G. Andersen1, Michael Kaminsky2,
Nathan Binkert3*, Niraj Tolia3*, Reinhard Munz1*,Parthasarathy Ranganathan3

1 Carnegie Mellon University
2 Intel Labs
3 HP Labs
*Work done while the author was at the specified institution.


This paper looks at systems design for consistent, durable, and safe memory management for future byte-addressable non-volatile (NV) memory. Specifically, we focus on how application-level interfaces need to change to accomodate this memory on the main memory bus and propose (1) a new NV-memory-aware memory allocator that incorporates wear leveling optimizations and stronger robustness to avoid data corruption—NVMalloc, (2) a new low-overhead mechanism for containing erroneous writes using an asynchronous implementation of mprotect, and (3) a new application interface to track and enforce update consistency at the processor cache level using cache line counters. Our proposed optimizations are designed holistically across the application, OS, and hardware layers.

We implement our optimizations and evaluate their benefits for realistic scenarios (including a simulation study of the hardware changes). Across three different evaluations—a stress microbenchmark, an in-memory B+ tree, and Memcached—our proposed memory allocator achieves better write distribution and robustness than existing allocators, with low fragmentation and overhead. Similarly, our evaluation shows that our interfaces for asynchronous memory protection and cache-level update consistency can achieve significant improvements in throughput compared to conservative approaches to enforcing safety, and competitive to designs with no support for improved safety.

Compared to prior work, our paper is, to the best of our knowledge, the first to propose a general-purpose and flexible approach to rethinking the interfaces across the application, OS, and hardware layers for future high performance NV memory systems.


FULL TR: pdf




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