PDL ABSTRACT

Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM

ISCA ’17, June 24-28, 2017, Toronto, ON, Canada

Rajat Kateja, Anirudh Badam*, Sriram Govindan*, Bikash Sharma*, Greg Ganger

Carnegie Mellon University
* Microsoft

http://www.pdl.cmu.edu/

Non-Volatile Memories (NVMs) can significantly improve the performance of data-intensive applications. A popular form of NVM is Battery-backed DRAM, which is available and in use today with DRAMs latency and without the endurance problems of emerging NVM technologies. Modern servers can be provisioned with up-to 4 TB of DRAM, and provisioning battery backup to write out such large memories is hard because of the large battery sizes and the added hardware and cooling costs. We present Viyojit, a system that exploits the skew in write working sets of applications to provision substantially smaller batteries while still ensuring durability for the entire DRAM capacity. Viyojit achieves this by bounding the number of dirty pages in DRAM based on the provisioned battery capacity and proactively writing out infrequently written pages to an SSD. Even for write-heavy workloads with less skew than we observe in analysis of real data center traces, Viyojit reduces the required battery capacity to 11% of the original size, with a performance overhead of 7-25%. Thus, Viyojit frees battery-backed DRAM from stunted growth of battery capacities and enables servers with terabytes of battery-backed DRAM.

FULL PAPER: pdf

 

 

 

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