PDL ABSTRACT

Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems

Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA 2013), Shenzhen, China, February 2013.

Reetuparna Das*, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar†, Mani Azimi†

Carnegie Mellon University
5000 Forbes Ave.
Pittsburgh, PA 15213

*University of Michigan
†Intel Labs

http://www.pdl.cmu.edu/

Future many-core processors are likely to concurrently execute a large number of diverse applications. How these applications are mapped to cores largely determines the interference between these applications in critical shared hardware resources. This paper proposes new application-to-core mapping policies to improve system performance by reducing interapplication interference in the on-chip network and memory controllers. The major new ideas of our policies are to: 1) map network-latency-sensitive applications to separate parts of the network from network-bandwidth-intensive applications such that the former can make fast progress without heavy interference from the latter, 2) map those applications that benefit more from being closer to the memory controllers close to these resources.

Our evaluations show that, averaged over 128 multiprogrammed workloads of 35 different benchmarks running on a 64-core system, our final application-to-core mapping policy improves system throughput by 16.7% over a state-of-the-art baseline, while also reducing system unfairness by 22.4% and average interconnect power consumption by 52.3%.

FULL PAPER: pdf

 

 

 

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