PDL ABSTRACT

Memory Power Management via Dynamic Voltage/Frequency Scaling

Proceedings of the 8th International Conference on Autonomic Computing (ICAC), Karlsruhe, Germany, June 2011.

Howard David*, Chris Fallin, Eugene Gorbatov*, Ulf R. Hanebutte*, Onur Mutlu

Carnegie Mellon University
5000 Forbes Ave.
Pittsburgh, PA 15213

*Intel Labs

http://www.pdl.cmu.edu/

Energy efficiency and energy-proportional computing have become a central focus in enterprise server architecture. As thermal and electrical constraints limit system power, and datacenter operators become more conscious of energy costs, energy efficiency becomes important across the whole system. There are many proposals to scale energy at the datacenter and server level. However, one significant component of server power, the memory system, remains largely unaddressed.

We propose memory dynamic voltage/ frequency scaling (DVFS) to address this problem, and evaluate a simple algorithm in a real system. As we show, in a typical server platform, memory consumes 19% of system power on average while running SPEC CPU2006 workloads. While increasing core counts demand more bandwidth and drive the memory frequency upward, many workloads require much less than peak bandwidth. These workloads suer minimal performance impact when memory frequency is reduced. When frequency reduces, voltage can be reduced as well.

We demonstrate a large opportunity for memory power reduction with a simple control algorithm that adjusts memory voltage and frequency based on memory bandwidth utilization. We evaluate memory DVFS in a real system, emulating reduced memory frequency by altering timing registers and using an analytical model to compute power reduction. With an average of 0.17% slowdown, we show 10.4% aver- age (20.5% max) memory power reduction, yielding 2.4% average (5.2% max) whole-system energy improvement.

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