PDL ABSTRACT

Design Guidelines for High Performance RDMA Systems

2016 USENIX Annual Technical Conference (USENIX ATC’16), June 22-24, 2016, Denver, CO.

Anuj Kalia, Michael Kaminsky†, David G. Andersen

Carnegie Mellon University
†Intel Labs

http://www.pdl.cmu.edu/

Modern RDMA hardware offers the potential for exceptional performance, but design choices including which RDMA operations to use and how to use them significantly affect observed performance. This paper lays out guidelines that can be used by system designers to navigate the RDMA design space. Our guidelines emphasize paying attention to low-level details such as individual PCIe transactions and NIC architecture. We empirically demonstrate how these guidelines can be used to improve the performance of RDMA-based systems: we design a networked sequencer that outperforms an existing design by 50x, and improve the CPU efficiency of a prior high-performance key-value store by 83%. We also present and evaluate several new RDMA optimizations and pitfalls, and discuss how they affect the design of RDMA systems.

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