header and data digest issue

["Bob Mastors" <bmastors@aciesnetworks.com>]

I think there is a problem with the current design of the
header and data digest.
There is a non-zero chance that an error could cause
the target to process a single pdu that has a header from
one pdu and data from a second pdu.

This type of error is undetectable by the target with the CRC32C
digests turned on.

For example:
        Initiator sends pdu 1 which contains header H1 and data D1
        Initiator sends pdu 2 which contains header H2 and data D2
        Target receives pdu 1 which contains header H1 and data D1
        Target receives pdu 2 which contains header H2 and data D1 (bad)
In this example the header and data digests will checksum correctly.
However the wrong data will be written to addresses indicated in H2.

There are three obvious places this error can occur:
        1. the initiator
        2. an intelligent router/switch
        3. the target

Not much can be done about initiator problems.
But I would like to detect problems introduced by the other areas.

I think it is actually likely that my target software will run
in an environment that produces this type of error.
Imagining how an intelligent router/switch or off-board iSCSI target
hardware might operate, it is probably only a single bit logic error
that could cause this type of error.

Maybe it is not appropriate to address this problem in the iSCSI spec
because I have described a problem that would not occur on the wire.
However iSCSI is the mechanism that allows more hardware and software
to be interposed between the SCSI initiator and the SCSI target.
iSCSI should not allow a single bit logic error in this additional
hardware and software to produce an undetectable error.

Bob