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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: header and data digest issueI do not believe a single bit error could cause what you suggested. The data is a stream of TCP bytes. TCP does not know the difference. Also these are not separate packets, there is no reason to think that there is any more probability of an error occurring at that DataSection boundary then any other place in the stream. To say that somehow, this same error caused a completely different Data section to have a like problem at its Data Section boundary, and that they would now get crossed at exactly that point, tells me it is a SW error, not a single bit error. . . . John L. Hufferd Senior Technical Staff Member (STSM) IBM/SSG San Jose Ca Main Office (408) 256-0403, Tie: 276-0403, eFax: (408) 904-4688 Home Office (408) 997-6136, Cell: (408) 499-9702 Internet address: hufferd@us.ibm.com "Bob Mastors" <bmastors@aciesnetworks.com>@ece.cmu.edu on 02/27/2002 08:48:58 AM Sent by: owner-ips@ece.cmu.edu To: "IPS" <ips@ece.cmu.edu> cc: Subject: header and data digest issue I think there is a problem with the current design of the header and data digest. There is a non-zero chance that an error could cause the target to process a single pdu that has a header from one pdu and data from a second pdu. This type of error is undetectable by the target with the CRC32C digests turned on. For example: Initiator sends pdu 1 which contains header H1 and data D1 Initiator sends pdu 2 which contains header H2 and data D2 Target receives pdu 1 which contains header H1 and data D1 Target receives pdu 2 which contains header H2 and data D1 (bad) In this example the header and data digests will checksum correctly. However the wrong data will be written to addresses indicated in H2. There are three obvious places this error can occur: 1. the initiator 2. an intelligent router/switch 3. the target Not much can be done about initiator problems. But I would like to detect problems introduced by the other areas. I think it is actually likely that my target software will run in an environment that produces this type of error. Imagining how an intelligent router/switch or off-board iSCSI target hardware might operate, it is probably only a single bit logic error that could cause this type of error. Maybe it is not appropriate to address this problem in the iSCSI spec because I have described a problem that would not occur on the wire. However iSCSI is the mechanism that allows more hardware and software to be interposed between the SCSI initiator and the SCSI target. iSCSI should not allow a single bit logic error in this additional hardware and software to produce an undetectable error. Bob
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