Parallel Data Laboratory

PDL Abstract Architecting Phase Change Memory as a Scalable DRAM Alternative Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009. Benjamin C. Lee1, Engin Ipek2, Onur Mutlu, Doug Burger3 Electrical & Computer Engineering Carnegie Mellon University 5000 Forbes Ave. Pittsburgh, PA 15213 1 Stanford University 2 University of Rochester 3 Microsoft Research http://www.pdl.cmu.edu/ Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM’s scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance. We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance. FULL PAPER: pdf PDL Abstract Architecting Phase Change Memory as a Scalable DRAM Alternative Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009. Benjamin C. Lee1, Engin Ipek2, Onur Mutlu, Doug Burger3 Electrical & Computer Engineering Carnegie Mellon University 5000 Forbes Ave. Pittsburgh, PA 15213 1 Stanford University 2 University of Rochester 3 Microsoft Research http://www.pdl.cmu.edu/ Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM’s scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance. We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance. FULL PAPER: pdf Parallel Data Laboratory

PARALLEL DATA LAB

PDL Abstract

Architecting Phase Change Memory as a Scalable DRAM Alternative

Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009.

Benjamin C. Lee¹, Engin Ipek², Onur Mutlu, Doug Burger³

Electrical & Computer Engineering
Carnegie Mellon University
5000 Forbes Ave.
Pittsburgh, PA 15213

¹ Stanford University
² University of Rochester
³ Microsoft Research

http://www.pdl.cmu.edu/

Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM’s scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance. We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.

FULL PAPER: pdf