PARALLEL DATA LAB 

PDL Abstract

A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory

45th International Symposium on Computer Architecture (ISCA), Los Angeles, CA, USA, June 2018.

Nandita Vijaykumar†§, Abhilasha Jain†, Diptesh Majumdar†, Kevin Hsieh†, Gennady Pekhimenko‡, Eiman Ebrahimi*, Nastaran Hajinazar^, Phillip B. Gibbons†, Onur Mutlu§†

† Carnegie Mellon University
‡ University of Toronto
* NVIDIA
^ Simon Fraser University
§ ETH Zürich

http://www.pdl.cmu.edu/

This paper makes a case for a new cross-layer interface, Expressive Memory (XMem), to communicate higher-level program semantics from the application to the system software and hardware architecture. XMem provides (i) a flexible and extensible abstraction, called an Atom, enabling the application to express key program semantics in terms of how the program accesses data and the attributes of the data itself, and (ii) new cross-layer interfaces to make the expressed higher-level information available to the underlying OS and architecture. By providing key information that is otherwise unavailable, XMem exposes a new, rich view of the program data to the OS and the dierent architectural components that optimize memory system performance (e.g., caches, memory controllers).

By bridging the semantic gap between the application and the underlying memory resources, XMem provides two key benefits. First, it enables architectural/system-level techniques to leverage key program semantics that are challenging to predict or infer. Second, it improves the efficacy and portability of software optimizations by alleviating the need to tune code for specific hardware resources (e.g., cache space). While XMem is designed to enhance and enable a wide range of memory optimizations, we demonstrate the benefits of XMem using two use cases: (i) improving the performance portability of softwarebased cache optimization by expressing the semantics of data locality in the optimization and (ii) improving the performance of OS-based page placement in DRAM by leveraging the semantics of data structures and their access properties.

FULL PAPER: pdf